1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and more particularly, to a non-volatile semiconductor memory device conducting programming/erasure by controlling electrons in a floating gate.
2. Description of the Related Art
A flash memory that is one type of a non-volatile semiconductor memory device carries out programming/erasure by controlling electrons in a floating gate. As used herein, introducing electron to a floating gate is referred to as “programming”. By such programming, a memory cell takes the logic value of “0”, and the threshold voltage of the memory cell transistor becomes higher. Drawing out electrons from a floating gate is referred to as “erasure”. By such erasure, the memory cell takes a logic value of “1”, and the threshold voltage of the memory cell transistor becomes lower.
In a flash memory, testing is conducted to verify whether such operations are effected properly within the specification value of the memory cell. Unintentional draw out or introduction of electrons may occur in a memory cell under various conditions and status. When electrons are drawn out or introduced, the threshold voltage of the memory cell transistor will be shifted, inducing the possibility of altering the logic value of the memory cell. In a flash memory, testing is conducted to verify whether such change in the logic value of a memory cell has occurred or not. Such testing is mainly divided into the three groups: expected value pattern readout test, erasure operation confirmation test, and erasure/programming repetitive test.
In an expected value pattern readout test, burn-in testing, bake testing, stress testing, and the like are conducted to verify whether the data in the memory cells have changed or not before and after these testing. Specifically, the entire region of the chip is read out for comparison with an expected value using a tester. Accordingly, any defective (NG) chips can be rejected by the threshold voltage shifting based on disturbance, accelerated testing, and the like.
In an erasure operation confirmation test, a normal erasure command is input to effect an erasure operation. If the erasure operation does not end within a specified time, that chip is rejected as falling the test. Specifically, the erasure time or the maximum value of erasure count is set at the tester side. Determination is made of failure at the tester side when the maximum value is surpassed.
In an erasure/programming repetitive test, program data, all “0” in particular, are loaded from an external source to a page buffer in the flash memory, and programming is initiated. When programming ends, erasure is conducted to set all the data in the memory cells to “1”. By repeating such programming and erasure, change in the threshold voltages of the memory cells is tested.
In order to shorten the time required for such testing, each operation of read out, programming, and erasure must be conducted as fast as possible by improving the performance or capability of the semiconductor chip. Furthermore, determination of the testing results must be made efficiently.
A non-volatile semiconductor memory device disclosed in Japanese Patent Laying-Open No. 2001-155500 includes a verify circuit, corresponding to a memory block, for comparing output data from a memory block with expected value data. Accordingly, verify testing can be executed concurrently for every memory block to increase the speed of the verify testing.
A non-volatile semiconductor memory device disclosed in Japanese Patent Laying-Open No. 09-259593 has the erasure operation stopped when the operation mode does not proceed to the next operation within a set period of time of a timer.
These non-volatile semiconductor memory devices allow for a shorter testing time. There are other non-volatile semiconductor memory devices capable of reducing the testing time.